[PATCH] D125602: [X86][AMX][fastalloc] Allocate tile register separately.

[LuoYuanke via Phabricator via llvm-commits]

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Allocating tile register in a separate pass have 3 benifits.

1. When spill tile register in fast register allocation, it would create

a virtual register for stride. The instruction that def the virtual
register is inserted after current instruction which is allocating
physical register, so fast register allocation won't access the new
instrution and the virtual register won't be allocated with physical
register.

2. When fill the shape information of tile configure, we need to know

the tile physical register. If the shape (row, column) is allocated with
physical register, the physical register may be re-defined before
writing it to stack. The re-def may happen during split or spill
registers. If the shape is in virtual register, there is no such
problem.
%al = 1
mov %al, %bl
%al = 2
store stack.cfg, %al ; config
ldtilecfg

3. Single configure may fail. In that case we can fallback to

multi-config and allocate tile register seperately, while leave other
registers be allocated by greedy RA.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125602

Files:
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/Target/X86/X86LowerAMXType.cpp
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Target/X86/X86TargetMachine.cpp
  llvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
  llvm/test/CodeGen/X86/AMX/amx-zero-config.ll

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