[PATCH] D125421: [TableGen] Add generation of argument register lists

[Bill Wendling via Phabricator via llvm-commits]

void updated this revision to Diff 429340.
void added a comment.

Avoid warning about zero-sized arrays:

  lib/Target/AArch64/AArch64GenCallingConv.inc:1266:64: warning: zero size arrays are an extension [-Wzero-length-array]
  const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = {  };


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125421/new/

https://reviews.llvm.org/D125421

Files:
  llvm/utils/TableGen/CallingConvEmitter.cpp

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