[llvm] 853fa8e - [RISCV] Address post-commit feedback from af5e09b

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-05-13T09:51:23-07:00
New Revision: 853fa8ee225edf2d0de94b0dcbd31bea916e825e

URL: https://github.com/llvm/llvm-project/commit/853fa8ee225edf2d0de94b0dcbd31bea916e825e
DIFF: https://github.com/llvm/llvm-project/commit/853fa8ee225edf2d0de94b0dcbd31bea916e825e.diff

LOG: [RISCV] Address post-commit feedback from af5e09b

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index acf5d37ce8b0..b3e6cd8a915a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -265,11 +265,11 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   }
 
   // Handle copy from csr
-  // TODO: Handle sysreg lookup generically and remove vlenb restriction.
-  if (RISCV::VCSRRegClass.contains(SrcReg) && SrcReg == RISCV::VLENB &&
+  if (RISCV::VCSRRegClass.contains(SrcReg) &&
       RISCV::GPRRegClass.contains(DstReg)) {
+    const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
     BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)
-      .addImm(RISCVSysReg::lookupSysRegByName("VLENB")->Encoding)
+      .addImm(RISCVSysReg::lookupSysRegByName(TRI.getName(SrcReg))->Encoding)
       .addReg(RISCV::X0);
     return;
   }