[llvm] 905eff4 - [x86] add test to show potential miscompile with undef value; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-05-13T10:55:14-04:00
New Revision: 905eff45a0af26cc0e877ddff846c97c77cead0c

URL: https://github.com/llvm/llvm-project/commit/905eff45a0af26cc0e877ddff846c97c77cead0c
DIFF: https://github.com/llvm/llvm-project/commit/905eff45a0af26cc0e877ddff846c97c77cead0c.diff

LOG: [x86] add test to show potential miscompile with undef value; NFC

This is based on:
c2a5a87500d92c

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-urem.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-urem.ll b/llvm/test/CodeGen/X86/combine-urem.ll
index 27c209aa6728..5c13315a250c 100644
--- a/llvm/test/CodeGen/X86/combine-urem.ll
+++ b/llvm/test/CodeGen/X86/combine-urem.ll
@@ -58,6 +58,23 @@ define <4 x i32> @combine_vec_urem_by_negone(<4 x i32> %x) {
   ret <4 x i32> %1
 }
 
+; Use PSLLI intrinsic to postpone the undef creation until after urem-by-constant expansion
+
+define <4 x i32> @combine_vec_urem_undef_by_negone(<4 x i32> %in) {
+; SSE-LABEL: combine_vec_urem_undef_by_negone:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_urem_undef_by_negone:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %x = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 0)
+  %y = urem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %y
+}
+
 ; fold (urem x, INT_MIN) -> (and x, ~INT_MIN)
 define i32 @combine_urem_by_minsigned(i32 %x) {
 ; CHECK-LABEL: combine_urem_by_minsigned: