[llvm] 98f82d6 - [X86] LowerStore - use is64BitVector() wrapper. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 13 07:30:32 PDT 2022
Author: Simon Pilgrim
Date: 2022-05-13T15:30:18+01:00
New Revision: 98f82d69bdef17932112235eab65c1ba085d10fd
URL: https://github.com/llvm/llvm-project/commit/98f82d69bdef17932112235eab65c1ba085d10fd
DIFF: https://github.com/llvm/llvm-project/commit/98f82d69bdef17932112235eab65c1ba085d10fd.diff
LOG: [X86] LowerStore - use is64BitVector() wrapper. NFCI.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6c0ec07e9841e..3ee8aa964f28e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25325,10 +25325,10 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
}
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- assert(StoreVT.isVector() && StoreVT.getSizeInBits() == 64 &&
- "Unexpected VT");
+ assert(StoreVT.is64BitVector() && "Unexpected VT");
assert(TLI.getTypeAction(*DAG.getContext(), StoreVT) ==
- TargetLowering::TypeWidenVector && "Unexpected type action!");
+ TargetLowering::TypeWidenVector &&
+ "Unexpected type action!");
EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), StoreVT);
StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, StoredVal,
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