[PATCH] D124284: [SLP]Try partial store vectorization if supported by target.
Dávid Bolvanský via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 13 05:26:51 PDT 2022
xbolva00 added inline comments.
================
Comment at: llvm/test/Transforms/SLPVectorizer/X86/arith-mul-load.ll:14
define void @add4(ptr noalias nocapture noundef %r, ptr noalias nocapture noundef readonly %a) {
; SSE-LABEL: @add4(
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RKSimon wrote:
> ABataev wrote:
> > RKSimon wrote:
> > > I'll investigate adding 32-bit vector load/store handling as well (it has the same costs as the codegen for 64-bit anyhow).
> > TTI does not report that it supports 32 bit stores.
> We never bothered to add it - we mainly use the 64-bit vector load/store to handle f64-i64 handling on 32-bit targets
Do you plan to add them?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D124284/new/
https://reviews.llvm.org/D124284
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