[llvm] 1b07bd9 - [X86] Add tests for vector widening with freeze(undef)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 13 04:12:34 PDT 2022
Author: Simon Pilgrim
Date: 2022-05-13T12:08:24+01:00
New Revision: 1b07bd9034bd44fc9b408a48a32ee6ef4b819784
URL: https://github.com/llvm/llvm-project/commit/1b07bd9034bd44fc9b408a48a32ee6ef4b819784
DIFF: https://github.com/llvm/llvm-project/commit/1b07bd9034bd44fc9b408a48a32ee6ef4b819784.diff
LOG: [X86] Add tests for vector widening with freeze(undef)
As noted on D103874, the 'no-op' vector widening intrinsics currently depend on undef shuffle mask indices, moving to poison we need to adjust this to reference a 'undefined' second vector operand, which will be a freeze(undef).
Added:
Modified:
llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/avx-intrinsics-x86.ll
llvm/test/CodeGen/X86/avx512-intrinsics.ll
llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
index 7e9a727e7230b..a4914c9d65c34 100644
--- a/llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
@@ -254,6 +254,17 @@ define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind {
ret <4 x double> %res
}
+define <4 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castpd128_pd256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <2 x double> undef
+ %res = shufflevector <2 x double> %a0, <2 x double> %a1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %res
+}
+
define <2 x double> @test_mm256_castpd256_pd128(<4 x double> %a0) nounwind {
; CHECK-LABEL: test_mm256_castpd256_pd128:
; CHECK: # %bb.0:
@@ -289,6 +300,17 @@ define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind {
ret <8 x float> %res
}
+define <8 x float> @test_mm256_castps128_ps256_freeze(<4 x float> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castps128_ps256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <4 x float> undef
+ %res = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x float> %res
+}
+
define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind {
; CHECK-LABEL: test_mm256_castps256_ps128:
; CHECK: # %bb.0:
@@ -308,6 +330,17 @@ define <4 x i64> @test_mm256_castsi128_si256(<2 x i64> %a0) nounwind {
ret <4 x i64> %res
}
+define <4 x i64> @test_mm256_castsi128_si256_freeze(<2 x i64> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castsi128_si256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <2 x i64> undef
+ %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i64> %res
+}
+
define <4 x double> @test_mm256_castsi256_pd(<4 x i64> %a0) nounwind {
; CHECK-LABEL: test_mm256_castsi256_pd:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll
index 8e48289c1042e..293d7fad7a6bb 100644
--- a/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll
@@ -1030,3 +1030,57 @@ define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
ret <2 x i64> %res
}
declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+
+define <4 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind {
+; AVX-LABEL: test_mm256_castpd128_pd256_freeze:
+; AVX: # %bb.0:
+; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: test_mm256_castpd128_pd256_freeze:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %a1 = freeze <2 x double> undef
+ %res = shufflevector <2 x double> %a0, <2 x double> %a1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x double> %res
+}
+
+
+define <8 x float> @test_mm256_castps128_ps256_freeze(<4 x float> %a0) nounwind {
+; AVX-LABEL: test_mm256_castps128_ps256_freeze:
+; AVX: # %bb.0:
+; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: test_mm256_castps128_ps256_freeze:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %a1 = freeze <4 x float> undef
+ %res = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x float> %res
+}
+
+
+define <4 x i64> @test_mm256_castsi128_si256_freeze(<2 x i64> %a0) nounwind {
+; AVX-LABEL: test_mm256_castsi128_si256_freeze:
+; AVX: # %bb.0:
+; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+;
+; AVX512VL-LABEL: test_mm256_castsi128_si256_freeze:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xc0,0x01]
+; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %a1 = freeze <2 x i64> undef
+ %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i64> %res
+}
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll
index 41e21e9b40c7b..12d47cef622be 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll
@@ -7492,6 +7492,85 @@ define <8 x i64> @test_x86_avx512_maskz_psrlv_q_512(<8 x i64> %a0, <8 x i64> %a1
declare <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64>, <8 x i64>) nounwind readnone
+
+define <8 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castpd128_pd256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <2 x double> undef
+ %res = shufflevector <2 x double> %a0, <2 x double> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ ret <8 x double> %res
+}
+
+
+define <8 x double> @test_mm256_castpd256_pd256_freeze(<4 x double> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castpd256_pd256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <4 x double> undef
+ %res = shufflevector <4 x double> %a0, <4 x double> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x double> %res
+}
+
+
+define <16 x float> @test_mm256_castps128_ps512_freeze(<4 x float> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castps128_ps512_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <4 x float> undef
+ %res = shufflevector <4 x float> %a0, <4 x float> %a1, <16x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+ ret <16 x float> %res
+}
+
+
+define <16 x float> @test_mm256_castps256_ps512_freeze(<8 x float> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castps256_ps512_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <8 x float> undef
+ %res = shufflevector <8 x float> %a0, <8 x float> %a1, <16x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x float> %res
+}
+
+
+define <8 x i64> @test_mm512_castsi128_si512_freeze(<2 x i64> %a0) nounwind {
+; CHECK-LABEL: test_mm512_castsi128_si512_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <2 x i64> undef
+ %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+ ret <8 x i64> %res
+}
+
+
+define <8 x i64> @test_mm512_castsi256_si512_pd256_freeze(<4 x i64> %a0) nounwind {
+; CHECK-LABEL: test_mm512_castsi256_si512_pd256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
+ %a1 = freeze <4 x i64> undef
+ %res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i64> %res
+}
+
+
define <16 x float> @bad_mask_transition(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> %d, <16 x float> %e, <16 x float> %f) {
; X64-LABEL: bad_mask_transition:
; X64: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll b/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
index 61b483329a4d9..f018ded1d7169 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
@@ -1215,3 +1215,41 @@ define <8 x half> @test_x86_avx512fp16_vcvtusi642sh(<8 x half> %arg0, i64 %arg1)
%res = fadd <8 x half> %res1, %res2
ret <8 x half> %res
}
+
+
+define <16 x half> @test_mm256_castph128_ph256_freeze(<8 x half> %a0) nounwind {
+; CHECK-LABEL: test_mm256_castph128_ph256_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %a1 = freeze <8 x half> undef
+ %res = shufflevector <8 x half> %a0, <8 x half> %a1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x half> %res
+}
+
+
+define <32 x half> @test_mm512_castph128_ph512_freeze(<8 x half> %a0) nounwind {
+; CHECK-LABEL: test_mm512_castph128_ph512_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %a1 = freeze <8 x half> undef
+ %res = shufflevector <8 x half> %a0, <8 x half> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <32 x half> %res
+}
+
+
+define <32 x half> @test_mm512_castph256_ph512_freeze(<16 x half> %a0) nounwind {
+; CHECK-LABEL: test_mm512_castph256_ph512_freeze:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %a1 = freeze <16 x half> undef
+ %res = shufflevector <16 x half> %a0, <16 x half> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ ret <32 x half> %res
+}
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