[PATCH] D122747: [NFC][ARM] Tests for Cortex-A57 and Cortex-A72 Fused AES Erratum

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

In D122747#3509495 <https://reviews.llvm.org/D122747#3509495>, @lenary wrote:

> I want to keep the number of llvm functions the same, as they cover a wide variety of control flow at a wide variety of data widths which the pass should cope with.
>
> One thing that I would like to cut down is the duplicated set of CHECK lines, one with scheduling and one without, but I'm not sure how to do that (the set with scheduling are there to test that `-mcpu=cortex-a55` enables the pass), I'm not sure of a better way of doing the same.

After a quick look, I can confirm that the ARM Backend seems to disregard `tune-cpu` metadata, the subtarget is initialized with TuneCPU equal to CPU, which makes this difficult. Still investigating whether `--enable-misched=false` will be enough.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122747/new/

https://reviews.llvm.org/D122747