[PATCH] D125310: [AArch64][RISCV][SelectionDAG] Support VECREDUCE_ADD mask operations

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Other than a minor nit the patch looks sensible.  However, there's a clear regression that needs resolving first.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5315
+  case ISD::VECREDUCE_ADD:
+    // If it is VECREDUCE_ADD mask operation then turn it to VECREDUCE_XOR
+    if (Operand.getValueType().getScalarType() == MVT::i1)
----------------
This comment doesn't offer any real value. None of the canonicalisation above and below this one are commented so perhaps no comment it necessary.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125310/new/

https://reviews.llvm.org/D125310