[PATCH] D125464: [AArch64] Preserve chain when lowering fixed length load to SVE (PR55281)
Nikita Popov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 12 07:04:20 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG44d85259d018: [AArch64] Preserve chain when lowering fixed length load to SVE (PR55281) (authored by nikic).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D125464/new/
https://reviews.llvm.org/D125464
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
@@ -15,7 +15,7 @@
; CHECK-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
; CHECK-NEXT: t18: nxv2i64,ch = LD1D_IMM<Mem:(volatile load (s512) from %ir.a)> t12, t2, TargetConstant:i64<0>, t0
; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i32<0>
-; CHECK-NEXT: t17: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r0)> t18, t12, TargetFrameIndex:i64<0>, TargetConstant:i64<0>, t0
+; CHECK-NEXT: t17: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r0)> t18, t12, TargetFrameIndex:i64<0>, TargetConstant:i64<0>, t18:1
; CHECK-NEXT: t16: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r1)> t18, t12, t8, TargetConstant:i64<0>, t17
; CHECK-NEXT: t10: ch = RET_ReallyLR t16
; CHECK-EMPTY:
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20140,22 +20140,23 @@
MemVT = MemVT.changeTypeToInteger();
}
- auto NewLoad = DAG.getMaskedLoad(
+ SDValue NewLoad = DAG.getMaskedLoad(
LoadVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(), Pg,
DAG.getUNDEF(LoadVT), MemVT, Load->getMemOperand(),
Load->getAddressingMode(), Load->getExtensionType());
+ SDValue Result = NewLoad;
if (VT.isFloatingPoint() && Load->getExtensionType() == ISD::EXTLOAD) {
EVT ExtendVT = ContainerVT.changeVectorElementType(
Load->getMemoryVT().getVectorElementType());
- NewLoad = getSVESafeBitCast(ExtendVT, NewLoad, DAG);
- NewLoad = DAG.getNode(AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, DL, ContainerVT,
- Pg, NewLoad, DAG.getUNDEF(ContainerVT));
+ Result = getSVESafeBitCast(ExtendVT, Result, DAG);
+ Result = DAG.getNode(AArch64ISD::FP_EXTEND_MERGE_PASSTHRU, DL, ContainerVT,
+ Pg, Result, DAG.getUNDEF(ContainerVT));
}
- auto Result = convertFromScalableVector(DAG, VT, NewLoad);
- SDValue MergedValues[2] = {Result, Load->getChain()};
+ Result = convertFromScalableVector(DAG, VT, Result);
+ SDValue MergedValues[2] = {Result, NewLoad.getValue(1)};
return DAG.getMergeValues(MergedValues, DL);
}
@@ -20203,19 +20204,20 @@
IsPassThruZeroOrUndef = true;
}
- auto NewLoad = DAG.getMaskedLoad(
+ SDValue NewLoad = DAG.getMaskedLoad(
ContainerVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(),
Mask, PassThru, Load->getMemoryVT(), Load->getMemOperand(),
Load->getAddressingMode(), Load->getExtensionType());
+ SDValue Result = NewLoad;
if (!IsPassThruZeroOrUndef) {
SDValue OldPassThru =
convertToScalableVector(DAG, ContainerVT, Load->getPassThru());
- NewLoad = DAG.getSelect(DL, ContainerVT, Mask, NewLoad, OldPassThru);
+ Result = DAG.getSelect(DL, ContainerVT, Mask, Result, OldPassThru);
}
- auto Result = convertFromScalableVector(DAG, VT, NewLoad);
- SDValue MergedValues[2] = {Result, Load->getChain()};
+ Result = convertFromScalableVector(DAG, VT, Result);
+ SDValue MergedValues[2] = {Result, NewLoad.getValue(1)};
return DAG.getMergeValues(MergedValues, DL);
}
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