[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 12 06:16:16 PDT 2022


dmgreen added a comment.

Thanks for the update. Have you tried a bootstrap to make sure it passes now?


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