[PATCH] D125308: [AArch64] Add missing HasNEON predicates to int->float patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

> I noticed that for signed conversions, some non-NEON instruction sequences are shorter. I don't know if the longer one is still faster on current architectures (the patterns date back to the initial backend import)

Yeah I believe the general idea was that going GRP->FPR is slower than keeping everything inside FPR registers. I was recently informed that those patterns should probably be guarded using the UseAlternateSExtLoadCVTF32 in the same way as other related patterns are.

This change LGTM though, in terms of NEON support. Thanks.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5028-5030
 }
 
+let Predicates = [HasNEON] in {
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Perhaps just extend the previous HasNeon block? I'm not sure that's clearer though.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5117
 // performIntToFpCombine.
+}
 
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Having a comment, `// Predicates = [HasNEON]` might be useful.


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