[PATCH] D119442: [NFC][SVE] Add more tests to CodeGen/AArch64/sve-fixed-length-reshuffle.ll

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 11 03:30:48 PDT 2022


sdesmalen added a comment.

The tests all seem valid, but it's a bit difficult to review this patch without knowing what it's really trying to test without really going through AArch64TargetLowering::ReconstructShuffle in detail. That function is quite big/complicated, so it's not trivial to spot whether anything is missing or redundant.
My main question is whether all the insert/extract-subvector tests need to test all the permutations of element type and subvector?



================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll:35
+  %el0 = extractelement <vscale x 4 x i1> %a, i32 0
+  %el1 = extractelement <vscale x 4 x i1> %a, i32 1
+  %v0 = insertelement <2 x i1> undef, i1 %el0, i32 0
----------------
Do we also want a test for extract elements 0 and 3, and inserting that into elements 0 and 1?


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll:67
+
+define <4 x i1> @reshuffle_v4i1_nxv8i1(<vscale x 8 x i1> %a) #0 {
+; CHECK-LABEL: reshuffle_v4i1_nxv8i1:
----------------
Do we need a `define <2 x i1> @reshuffle_v2i1_nxv8i1(..) ` as well?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119442/new/

https://reviews.llvm.org/D119442



More information about the llvm-commits mailing list