[PATCH] D125359: [RISCV][LegalizeVectorTypes] Enable WidenVecRes_SETCC work for scalable vector
WangLian via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 11 01:29:45 PDT 2022
Jimerlife created this revision.
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Replace getVectorNumElements with getVectorElementCount to enable WidenVecRes_SETCC work for scalable vector.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125359
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
Index: llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
+++ llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
@@ -4,6 +4,40 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
+define <vscale x 3 x i1> @icmp_eq_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmseq.vv v0, v8, v9
+; CHECK-NEXT: ret
+ %vc = icmp eq <vscale x 3 x i8> %va, %vb
+ ret <vscale x 3 x i1> %vc
+}
+
+define <vscale x 3 x i1> @icmp_eq_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmseq.vx v0, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
+ %vc = icmp eq <vscale x 3 x i8> %va, %splat
+ ret <vscale x 3 x i1> %vc
+}
+
+define <vscale x 3 x i1> @icmp_eq_xv_nxv3i8(<vscale x 3 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv3i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vmseq.vx v0, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
+ %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
+ %vc = icmp eq <vscale x 3 x i8> %splat, %va
+ ret <vscale x 3 x i1> %vc
+}
+
define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-LABEL: icmp_eq_vv_nxv8i8:
; CHECK: # %bb.0:
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5215,13 +5215,13 @@
N->getOperand(0).getValueType().isVector() &&
"Operands must be vectors");
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
+ ElementCount WidenEC = WidenVT.getVectorElementCount();
SDValue InOp1 = N->getOperand(0);
EVT InVT = InOp1.getValueType();
assert(InVT.isVector() && "can not widen non-vector type");
EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
- InVT.getVectorElementType(), WidenNumElts);
+ InVT.getVectorElementType(), WidenEC);
// The input and output types often differ here, and it could be that while
// we'd prefer to widen the result type, the input operands have been split.
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