[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Yeah I think the issue is that @cttztrunc should be doing `and 0x3f`, not `and 0x1f`.

We should really have caught that, but I was relying too much on a verification script that didn't catch it due to the way rbit is specified. Which reminds me that we should really be supporting ctlz too for the same transform, but perhaps that's best left to a followup.


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