[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

Tue May 10 05:49:27 PDT 2022

lenary added a comment.

Ack to all the comment clarifications, will update patch with those soon (probably tomorrow).

================
Comment at: llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp:146
+  case ARM::VMVNd:
+  case ARM::VMVNq:
+  // VMOV of 64-bit value between D registers (when condition = al)
----------------
dmgreen wrote:
> Perhaps add these, if they are safe:
> VBICd/q
> VBICi's, VORRi's
> VBIF/VBIT/VBSL/VBSP
> VCEQ/VCNE/etc?
> VDUP? VEXT?
> VMVN imm equivalents of VMOV's
> VREV's?
> VSHL's, VSHR's?
> I'm not sure if they will be very useful, but they are the kind of instructions that may come up in aes algorithms.
I'm very keen to avoid scope-creep on this patch, so I'm going to push back on this comment.

We know this list as given is safe (and have had internal confirmation). I've sent a new email internally with your list of instructions, to find out of they're safe too, but I'd like any answer to that to be part of a follow-up patch rather than blocking this patch for yet longer.

I believe what I have today is correct, even if the list is not optimal for all expected AES code sequences.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119720/new/

https://reviews.llvm.org/D119720