[PATCH] D125261: [AMDGPU] gfx11 subtarget features & early tests

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

LGTM also, I am just double checking tests, might add a few more comments soon.



================
Comment at: llvm/lib/Target/AMDGPU/GCNSubtarget.h:708-709
 
+  bool hasDot8Insts() const { return HasDot8Insts; }
+
   bool hasMAIInsts() const {
----------------
Can you use same line break as above? clang-format did this probably.


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir:20-31
-    %5:vgpr(<2 x s16>) = G_BITCAST %0(s32)
-
-    ; CHECK: [[UNDEF0:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; CHECK: [[UNDEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; CHECK: EXP 1, %0, %0, [[UNDEF1]], [[UNDEF0]], 0, 1, 15, implicit $exec
-    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), 1, 15, %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), 0, 0
-
----------------
What happened here? No need to delete.


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir:935-956
     ; GFX10-LABEL: name: load_flat_s32_from_1_gep_2047
     ; GFX10: liveins: $vgpr0_vgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
     ; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2047, implicit $exec
     ; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
----------------
This is interesting test change, which patch allows offset fold for this?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125261/new/

https://reviews.llvm.org/D125261