[llvm] 17a8a1b - [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation
Lian Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue May 10 01:54:08 PDT 2022
Author: Lian Wang
Date: 2022-05-10T08:52:48Z
New Revision: 17a8a1bb7126a7c1b0bc629d9299f2e5ae6db3f1
URL: https://github.com/llvm/llvm-project/commit/17a8a1bb7126a7c1b0bc629d9299f2e5ae6db3f1
DIFF: https://github.com/llvm/llvm-project/commit/17a8a1bb7126a7c1b0bc629d9299f2e5ae6db3f1.diff
LOG: [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D125206
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index fc3a19f4a9f59..509ac82ea665c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5311,6 +5311,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (Operand.getValueType().getScalarType() == MVT::i1)
return getNOT(DL, Operand, Operand.getValueType());
break;
+ case ISD::VECREDUCE_ADD:
+ // If it is VECREDUCE_ADD mask operation then turn it to VECREDUCE_XOR
+ if (Operand.getValueType().getScalarType() == MVT::i1)
+ return getNode(ISD::VECREDUCE_XOR, DL, VT, Operand);
+ break;
case ISD::VECREDUCE_SMIN:
case ISD::VECREDUCE_UMAX:
if (Operand.getValueType().getScalarType() == MVT::i1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
index d5e9d7d8fd14c..77f18921cf75c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
@@ -116,6 +116,22 @@ define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
+
+define signext i1 @vreduce_add_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
@@ -217,6 +233,20 @@ define signext i1 @vreduce_smin_v2i1(<2 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
+
+define signext i1 @vreduce_add_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
define signext i1 @vreduce_or_v4i1(<4 x i1> %v) {
@@ -318,6 +348,20 @@ define signext i1 @vreduce_smin_v4i1(<4 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
+
+define signext i1 @vreduce_add_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
define signext i1 @vreduce_or_v8i1(<8 x i1> %v) {
@@ -419,6 +463,20 @@ define signext i1 @vreduce_smin_v8i1(<8 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
+
+define signext i1 @vreduce_add_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
define signext i1 @vreduce_or_v16i1(<16 x i1> %v) {
@@ -520,6 +578,20 @@ define signext i1 @vreduce_smin_v16i1(<16 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
+
+define signext i1 @vreduce_add_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
define signext i1 @vreduce_or_v32i1(<32 x i1> %v) {
@@ -691,6 +763,30 @@ define signext i1 @vreduce_smin_v32i1(<32 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
+
+define signext i1 @vreduce_add_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_add_v32i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT: vmxor.mm v8, v0, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: neg a0, a0
+; LMULMAX1-NEXT: ret
+;
+; LMULMAX8-LABEL: vreduce_add_v32i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 32
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: neg a0, a0
+; LMULMAX8-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
define signext i1 @vreduce_or_v64i1(<64 x i1> %v) {
@@ -875,3 +971,29 @@ define signext i1 @vreduce_smin_v64i1(<64 x i1> %v) {
%red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
ret i1 %red
}
+
+declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
+
+define signext i1 @vreduce_add_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_add_v64i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; LMULMAX1-NEXT: vmxor.mm v8, v8, v10
+; LMULMAX1-NEXT: vmxor.mm v9, v0, v9
+; LMULMAX1-NEXT: vmxor.mm v8, v9, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: neg a0, a0
+; LMULMAX1-NEXT: ret
+;
+; LMULMAX8-LABEL: vreduce_add_v64i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 64
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: neg a0, a0
+; LMULMAX8-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v)
+ ret i1 %red
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
index 9ec56f98e6941..24f756763bdf7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
@@ -103,6 +103,20 @@ define signext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1>)
+
+define signext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)
define signext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {
@@ -204,6 +218,20 @@ define signext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1>)
+
+define signext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1>)
define signext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {
@@ -305,6 +333,20 @@ define signext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1>)
+
+define signext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1>)
define signext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {
@@ -406,6 +448,20 @@ define signext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1>)
+
+define signext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
define signext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {
@@ -507,6 +563,20 @@ define signext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1>)
+
+define signext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>)
define signext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {
@@ -608,6 +678,20 @@ define signext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {
ret i1 %red
}
+declare i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1>)
+
+define signext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)
+ ret i1 %red
+}
+
declare i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1>)
define signext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {
@@ -708,3 +792,17 @@ define signext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {
%red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
}
+
+declare i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1>)
+
+define signext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: ret
+ %red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)
+ ret i1 %red
+}
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