[PATCH] D125261: [AMDGPU] gfx11 subtarget features & early tests

Joe Nash via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 9 12:30:18 PDT 2022 

Joe_Nash created this revision.
Herald added subscribers: jsilvanus, hsmhsm, foad, wenlei, kerbowa, javed.absar, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, dylanmckay, arsenm, qcolombet.
Herald added a project: All.
Joe_Nash requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Tablegen definitions for subtarget features and cpp predicate functions to
access the features.
New Sub-TargetProcessors and common latencies.
Simple changes to MIR codegen tests which pass on gfx11 because they have the
same output as previous subtargets or operate on pseudo instructions which
are reused from previous subtargets.

Contributors:
Jay Foad <jay.foad at amd.com>
Petar Avramovic <Petar.Avramovic at amd.com>

Patch 4/N for upstreaming of AMDGPU gfx11 architecture

Depends on D124538 <https://reviews.llvm.org/D124538>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125261

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/lib/Target/AMDGPU/GCNProcessors.td
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
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  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
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  llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
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  llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
  llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir

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