[PATCH] D125247: [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.
Hendrik Greving via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 9 10:49:00 PDT 2022
hgreving created this revision.
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Adds MVT::v128i2, MVT::v64i4, and implied MVT::i2, MVT::i4 to support
for downstream targets.
Keeps MVT::i2, MVT::i4 lowering actions to `expand`, which should be
removed once target explicitly set its action.
Adjusts the remaining 11 lit tests to reflect slightly different
behavior during DAG combine.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125247
Files:
llvm/include/llvm/CodeGen/ValueTypes.td
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/IR/Function.cpp
llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
llvm/test/CodeGen/X86/bitreverse.ll
llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
llvm/test/TableGen/intrinsic-pointer-to-any.td
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/IntrinsicEmitter.cpp
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