[llvm] 3f64f03 - [CodeGen] Clarify the semantics of ADDCARRY/SUBCARRY

Kazu Hirata via llvm-commits llvm-commits at lists.llvm.org
Mon May 9 10:17:06 PDT 2022


Author: Kazu Hirata
Date: 2022-05-09T10:17:00-07:00
New Revision: 3f64f0328941c6ef13ce9d425f2a52061d774b92

URL: https://github.com/llvm/llvm-project/commit/3f64f0328941c6ef13ce9d425f2a52061d774b92
DIFF: https://github.com/llvm/llvm-project/commit/3f64f0328941c6ef13ce9d425f2a52061d774b92.diff

LOG: [CodeGen] Clarify the semantics of ADDCARRY/SUBCARRY

This patch clarifies the semantics of ADDCARRY/SUBCARRY, specifically
stating that both the incoming and outgoing carries are active high.

Differential Revision: https://reviews.llvm.org/D125130

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/ISDOpcodes.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index d57756b30291a..6ceb309817737 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -281,12 +281,25 @@ enum NodeType {
 
   /// Carry-using nodes for multiple precision addition and subtraction.
   /// These nodes take three operands: The first two are the normal lhs and
-  /// rhs to the add or sub, and the third is a boolean indicating if there
-  /// is an incoming carry. These nodes produce two results: the normal
-  /// result of the add or sub, and the output carry so they can be chained
-  /// together. The use of this opcode is preferable to adde/sube if the
-  /// target supports it, as the carry is a regular value rather than a
-  /// glue, which allows further optimisation.
+  /// rhs to the add or sub, and the third is a boolean value that is 1 if and
+  /// only if there is an incoming carry/borrow. These nodes produce two
+  /// results: the normal result of the add or sub, and a boolean value that is
+  /// 1 if and only if there is an outgoing carry/borrow.
+  ///
+  /// Care must be taken if these opcodes are lowered to hardware instructions
+  /// that use the inverse logic -- 0 if and only if there is an
+  /// incoming/outgoing carry/borrow.  In such cases, you must preserve the
+  /// semantics of these opcodes by inverting the incoming carry/borrow, feeding
+  /// it to the add/sub hardware instruction, and then inverting the outgoing
+  /// carry/borrow.
+  ///
+  /// The use of these opcodes is preferable to adde/sube if the target supports
+  /// it, as the carry is a regular value rather than a glue, which allows
+  /// further optimisation.
+  ///
+  /// These opcodes are 
diff erent from [US]{ADD,SUB}O in that ADDCARRY/SUBCARRY
+  /// consume and produce a carry/borrow, whereas [US]{ADD,SUB}O produce an
+  /// overflow.
   ADDCARRY,
   SUBCARRY,
 


        


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