[PATCH] D125215: [AArch64][SVE] Improve codegen when extracting first lane of active lane mask
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 9 03:56:13 PDT 2022
david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.
LGTM! Thanks for the codegen improvement @RosieSumpter. :)
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14654
+ N.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilelt ||
+ N.getConstantOperandVal(0) == Intrinsic::get_active_lane_mask)))
return true;
----------------
nit: Could you add a short comment here explaining that get_active_lane_mask is lowered to a whilelo instruction?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D125215/new/
https://reviews.llvm.org/D125215
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