[PATCH] D123394: [CodeGen] Late cleanup of redundant address/immediate definitions.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa added a comment.

In D123394#3499422 <https://reviews.llvm.org/D123394#3499422>, @nemanjai wrote:

> This is fine from a PPC perspective. What would make more of an impact would be the ability to common partial immediate materializations such as happen in prologue/epilogue when a stack frame is very large. Perhaps this can be extended to do that in the future. It would eliminate things like:
>
>   lis 11, 16
>   ori 11, 11, 256 
>   stxvx 53, 31, 11                        # 16-byte Folded Spill
>   lis 11, 16
>   ori 11, 11, 272 
>   stxvx 54, 31, 11                        # 16-byte Folded Spill
>   lis 11, 16
>   ori 11, 11, 288 
>   stxvx 55, 31, 11                        # 16-byte Folded Spill
>   lis 11, 16
>   ori 11, 11, 304 
>   stxvx 56, 31, 11                        # 16-byte Folded Spill
>
> Of course, that would involve changing the subsequent `ori` instructions to `addi` and would likely be very PPC-specific. I just bring it up here in case SystemZ has the same issue.

That's a good point - my idea so far about that is to try to use a postRA pseudo for e.g. an immediate load requiring two target instructions so that they can be handled just the same way during this pass. Alternatively, one could as you say probably extend this current algorithm to have some kind of "look-ahead" or something so that it could recognize e.g. pairs of instructions as well. That is a bit more complex, though... I will try pseudo on SystemZ and see how it goes with 32-bit immediate loads.

So you did not get any significant results on SPEC with this patch yet?

I checked the compile time and realized that I have to work on that a bit as I see a bit of slowdowns on some files.


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