[llvm] 800d36c - [DAG] Only perform the fold (A-B)+(C-D) --> (A+C)-(B+D) when both inner subs have one use

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-05-08T13:51:58+01:00
New Revision: 800d36cf32367a633bc24f668189365d63894f8c

URL: https://github.com/llvm/llvm-project/commit/800d36cf32367a633bc24f668189365d63894f8c
DIFF: https://github.com/llvm/llvm-project/commit/800d36cf32367a633bc24f668189365d63894f8c.diff

LOG: [DAG] Only perform the fold (A-B)+(C-D) --> (A+C)-(B+D) when both inner subs have one use

Fixes #51381

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/X86/combine-add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2bcd917d3304..1b84ad0efcc7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2518,7 +2518,8 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
                        N1.getOperand(1));
 
   // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
-  if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
+  if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && 
+      N0->hasOneUse() && N1->hasOneUse()) {
     SDValue N00 = N0.getOperand(0);
     SDValue N01 = N0.getOperand(1);
     SDValue N10 = N1.getOperand(0);

diff  --git a/llvm/test/CodeGen/X86/combine-add.ll b/llvm/test/CodeGen/X86/combine-add.ll
index 413a7a26bb0b..d740cfe8ce19 100644
--- a/llvm/test/CodeGen/X86/combine-add.ll
+++ b/llvm/test/CodeGen/X86/combine-add.ll
@@ -224,7 +224,7 @@ define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32>
   ret <4 x i32> %3
 }
 
-; FIXME: missing oneuse limit on fold
+; Check for oneuse limit on fold
 define void @PR52039(<8 x i32>* %pa, <8 x i32>* %pb) {
 ; SSE-LABEL: PR52039:
 ; SSE:       # %bb.0:
@@ -245,22 +245,17 @@ define void @PR52039(<8 x i32>* %pa, <8 x i32>* %pb) {
 ;
 ; AVX1-LABEL: PR52039:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vmovdqu (%rdi), %xmm0
-; AVX1-NEXT:    vmovdqu 16(%rdi), %xmm1
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [10,10,10,10]
-; AVX1-NEXT:    vpsubd %xmm0, %xmm2, %xmm3
-; AVX1-NEXT:    vpsubd %xmm1, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddd %xmm1, %xmm1, %xmm4
-; AVX1-NEXT:    vpaddd %xmm4, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm4
-; AVX1-NEXT:    vpaddd %xmm4, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [30,30,30,30]
-; AVX1-NEXT:    vpsubd %xmm0, %xmm4, %xmm0
-; AVX1-NEXT:    vpsubd %xmm1, %xmm4, %xmm1
-; AVX1-NEXT:    vmovdqu %xmm2, 16(%rsi)
-; AVX1-NEXT:    vmovdqu %xmm3, (%rsi)
-; AVX1-NEXT:    vmovdqu %xmm1, 16(%rdi)
-; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
+; AVX1-NEXT:    vmovdqa {{.*#+}} xmm0 = [10,10,10,10]
+; AVX1-NEXT:    vpsubd 16(%rdi), %xmm0, %xmm1
+; AVX1-NEXT:    vpsubd (%rdi), %xmm0, %xmm0
+; AVX1-NEXT:    vpaddd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpaddd %xmm1, %xmm1, %xmm3
+; AVX1-NEXT:    vpaddd %xmm3, %xmm1, %xmm3
+; AVX1-NEXT:    vmovdqu %xmm1, 16(%rsi)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rsi)
+; AVX1-NEXT:    vmovdqu %xmm3, 16(%rdi)
+; AVX1-NEXT:    vmovdqu %xmm2, (%rdi)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: PR52039: