[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 427890.
RKSimon edited the summary of this revision.
RKSimon added a comment.

rebase

@craig.topper What do you think I should do about the lost RISCV gorc2 fold?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124839/new/

https://reviews.llvm.org/D124839

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  llvm/test/CodeGen/X86/load-local-v3i129.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll

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