[PATCH] D122769: [RISCV] Add a prepass to vsetvli insertion to propagate VLMAX vsetvli to the instructions.

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Taking another look at this triggered by our offline chat.

I can't help but think the forward direction here is a bit awkward.  It would seem more natural to visit all the instructions with VL operands, and then check for the VReg which defines it whether we could prove it be equivalent to VLMAX.  Doing this either as a pre-pass, or maybe even inside getInfoForVSETVLI does seem to be worthwhile as it could eliminate inserted vsetvlis.  On the other hand, a post-pass could be easier to test (via explicit vsetvli tests), and might catch some intrinsic cases.

In short, I don't have strong opinions on pre-vs-post, but might encourage working back from the consumer instruction instead of forward.

Hm, just a thought, if we are working backwards in a pre-pass this starts looking like a dag combine?  Would we benefit from doing this there instead?


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https://reviews.llvm.org/D122769