[llvm] d955010 - Automatically generate CodeGen/X86/sse-align-*.ll test cases. NFC

Amaury Séchet via llvm-commits llvm-commits at lists.llvm.org
Fri May 6 08:51:15 PDT 2022


Author: Amaury Séchet
Date: 2022-05-06T15:44:50Z
New Revision: d955010d8dfb371650450c4dc44d8543d2e206f5

URL: https://github.com/llvm/llvm-project/commit/d955010d8dfb371650450c4dc44d8543d2e206f5
DIFF: https://github.com/llvm/llvm-project/commit/d955010d8dfb371650450c4dc44d8543d2e206f5.diff

LOG: Automatically generate CodeGen/X86/sse-align-*.ll test cases. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/sse-align-0.ll
    llvm/test/CodeGen/X86/sse-align-1.ll
    llvm/test/CodeGen/X86/sse-align-10.ll
    llvm/test/CodeGen/X86/sse-align-2.ll
    llvm/test/CodeGen/X86/sse-align-3.ll
    llvm/test/CodeGen/X86/sse-align-4.ll
    llvm/test/CodeGen/X86/sse-align-7.ll
    llvm/test/CodeGen/X86/sse-align-9.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/sse-align-0.ll b/llvm/test/CodeGen/X86/sse-align-0.ll
index 54c89ea411a4c..6d194f13ceb31 100644
--- a/llvm/test/CodeGen/X86/sse-align-0.ll
+++ b/llvm/test/CodeGen/X86/sse-align-0.ll
@@ -1,12 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
-; CHECK-NOT:     mov
 
 define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mulps (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %t = load <4 x float>, <4 x float>* %p
   %z = fmul <4 x float> %t, %x
   ret <4 x float> %z
 }
+
 define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mulpd (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %t = load <2 x double>, <2 x double>* %p
   %z = fmul <2 x double> %t, %x
   ret <2 x double> %z

diff  --git a/llvm/test/CodeGen/X86/sse-align-1.ll b/llvm/test/CodeGen/X86/sse-align-1.ll
index f58e1204d5262..0fc3ce3500f77 100644
--- a/llvm/test/CodeGen/X86/sse-align-1.ll
+++ b/llvm/test/CodeGen/X86/sse-align-1.ll
@@ -9,6 +9,7 @@ define <4 x float> @foo(<4 x float>* %p) nounwind {
   %t = load <4 x float>, <4 x float>* %p
   ret <4 x float> %t
 }
+
 define <2 x double> @bar(<2 x double>* %p) nounwind {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0:

diff  --git a/llvm/test/CodeGen/X86/sse-align-10.ll b/llvm/test/CodeGen/X86/sse-align-10.ll
index 48e405d792edc..16c1b776478a8 100644
--- a/llvm/test/CodeGen/X86/sse-align-10.ll
+++ b/llvm/test/CodeGen/X86/sse-align-10.ll
@@ -1,9 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define <2 x i64> @bar(<2 x i64>* %p) nounwind {
 ; CHECK-LABEL: bar:
-; CHECK: movups
-; CHECK-NOT: movups
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movups (%rdi), %xmm0
+; CHECK-NEXT:    retq
   %t = load <2 x i64>, <2 x i64>* %p, align 8
   ret <2 x i64> %t
 }

diff  --git a/llvm/test/CodeGen/X86/sse-align-2.ll b/llvm/test/CodeGen/X86/sse-align-2.ll
index af548be6c051e..501f7af340d22 100644
--- a/llvm/test/CodeGen/X86/sse-align-2.ll
+++ b/llvm/test/CodeGen/X86/sse-align-2.ll
@@ -1,21 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=penryn | FileCheck %s
 
 define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movups (%rdi), %xmm1
+; CHECK-NEXT:    mulps %xmm1, %xmm0
+; CHECK-NEXT:    retq
   %t = load <4 x float>, <4 x float>* %p, align 4
   %z = fmul <4 x float> %t, %x
   ret <4 x float> %z
 }
 
-; CHECK-LABEL: foo:
-; CHECK: movups
-; CHECK: ret
-
 define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movupd (%rdi), %xmm1
+; CHECK-NEXT:    mulpd %xmm1, %xmm0
+; CHECK-NEXT:    retq
   %t = load <2 x double>, <2 x double>* %p, align 8
   %z = fmul <2 x double> %t, %x
   ret <2 x double> %z
 }
-
-; CHECK-LABEL: bar:
-; CHECK: movupd
-; CHECK: ret

diff  --git a/llvm/test/CodeGen/X86/sse-align-3.ll b/llvm/test/CodeGen/X86/sse-align-3.ll
index b6b0471e913f4..d09eddd0bbab7 100644
--- a/llvm/test/CodeGen/X86/sse-align-3.ll
+++ b/llvm/test/CodeGen/X86/sse-align-3.ll
@@ -1,15 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
-; CHECK-NOT:     movapd
-; CHECK:     movaps
-; CHECK-NOT:     movapd
-; CHECK:     movaps
-; CHECK-NOT:     movap
 
 define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movaps %xmm0, (%rdi)
+; CHECK-NEXT:    retq
   store <4 x float> %x, <4 x float>* %p
   ret void
 }
+
 define void @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movaps %xmm0, (%rdi)
+; CHECK-NEXT:    retq
   store <2 x double> %x, <2 x double>* %p
   ret void
 }

diff  --git a/llvm/test/CodeGen/X86/sse-align-4.ll b/llvm/test/CodeGen/X86/sse-align-4.ll
index cc924b930d806..dbc90769a0826 100644
--- a/llvm/test/CodeGen/X86/sse-align-4.ll
+++ b/llvm/test/CodeGen/X86/sse-align-4.ll
@@ -9,6 +9,7 @@ define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
   store <4 x float> %x, <4 x float>* %p, align 4
   ret void
 }
+
 define void @bar(<2 x double>* %p, <2 x double> %x) nounwind {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0:

diff  --git a/llvm/test/CodeGen/X86/sse-align-7.ll b/llvm/test/CodeGen/X86/sse-align-7.ll
index e55d5859560e8..226a8b8a266a8 100644
--- a/llvm/test/CodeGen/X86/sse-align-7.ll
+++ b/llvm/test/CodeGen/X86/sse-align-7.ll
@@ -1,8 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
-; CHECK:     movaps
-; CHECK-NOT:     movaps
 
 define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movaps %xmm0, (%rdi)
+; CHECK-NEXT:    retq
   store <2 x i64> %x, <2 x i64>* %p
   ret void
 }

diff  --git a/llvm/test/CodeGen/X86/sse-align-9.ll b/llvm/test/CodeGen/X86/sse-align-9.ll
index d39e5d997990a..99aae9d3e5fa3 100644
--- a/llvm/test/CodeGen/X86/sse-align-9.ll
+++ b/llvm/test/CodeGen/X86/sse-align-9.ll
@@ -9,6 +9,7 @@ define <4 x float> @foo(<4 x float>* %p) nounwind {
   %t = load <4 x float>, <4 x float>* %p, align 4
   ret <4 x float> %t
 }
+
 define <2 x double> @bar(<2 x double>* %p) nounwind {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0:


        


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