[PATCH] D125021: [RISCV] Fix VSETVLI insertion by syncing phases 2 and 3

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir:856
   ; CHECK-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[PHI]]
-  ; CHECK-NEXT:   dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
   ; CHECK-NEXT:   [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], killed [[ADD]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
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This is a bug, but I'm not yet sure if it's dormant and exposed by this patch or actually caused by it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D125021/new/

https://reviews.llvm.org/D125021