[PATCH] D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D113291#3495933 <https://reviews.llvm.org/D113291#3495933>, @djtodoro wrote:

> Thanks!
>
> In D113291#3493276 <https://reviews.llvm.org/D113291#3493276>, @xbolva00 wrote:
>
>> How hard is to add x86 support?
>
> Is it even worth of implementing it for x86?

Yes. Intel CPUs from about 2013 have a TZCNT instruction.


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