[PATCH] D125075: [X86][AMX] Multiple configure for AMX register.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke created this revision.
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The previous solution depends on variable name to record the shape
information. However it is not reliable, because in release build
compiler would not set the variable name. It can be accomplished with an
additional option `fno-discard-value-names`, but it is not acceptable
for users.
This patch is to preconfigure the tile register with machine
instruction. It follow the same way what sigle configure does. In the
future we can fall back to multiple configure when single configure
fails due to the shape dependency issue.
The algorithm to configure the tile register is simple in the patch. We
may improve it in the future. It configure tile register based on basic
block. Compiler would spill the tile register if it live out the basic
block. After the configure there should be no spill across tile
confgiure in the register alloction. Just like fast register allocation
the algorithm walk the instruction in reverse order. When the shape
dependency doesn't meet, it insert ldtilecfg after the last instruction
that define the shape.
In post configuration compiler also walk the basic block to collect the
physical tile register number and generate instruction to fill the stack
slot for the correponding shape information.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125075

Files:
  llvm/lib/Target/X86/CMakeLists.txt
  llvm/lib/Target/X86/X86.h
  llvm/lib/Target/X86/X86FastPreTileConfig.cpp
  llvm/lib/Target/X86/X86FastTileConfig.cpp
  llvm/lib/Target/X86/X86TargetMachine.cpp
  llvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
  llvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
  llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
  llvm/test/CodeGen/X86/O0-pipeline.ll

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