[PATCH] D125067: [RISCV] Add RISCVISD::FCLASS_VL.
Han-Kuan Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 5 19:49:55 PDT 2022
HanKuanChen created this revision.
HanKuanChen added reviewers: craig.topper, frasercrmck.
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Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125067
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -97,6 +97,13 @@
def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>;
def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>;
+def riscv_fclass_vl : SDNode<"RISCVISD::FCLASS_VL",
+ SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
+ SDTCisFP<1>, SDTCisVec<1>,
+ SDTCisSameSizeAs<0, 1>,
+ SDTCVecEltisVT<2, i1>,
+ SDTCisSameNumEltsAs<0, 2>,
+ SDTCisVT<3, XLenVT>]>>;
def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
@@ -1471,6 +1478,12 @@
VLOpFrag),
(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
+
+ // 14.14. Vector Floating-Point Classify Instruction
+ def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask),
+ VLOpFrag),
+ (!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX)
+ vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
}
foreach fvti = AllFloatVectors in {
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -227,6 +227,7 @@
FNEG_VL,
FABS_VL,
FSQRT_VL,
+ FCLASS_VL,
FMA_VL,
FCOPYSIGN_VL,
SMIN_VL,
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11161,6 +11161,7 @@
NODE_NAME_CASE(FNEG_VL)
NODE_NAME_CASE(FABS_VL)
NODE_NAME_CASE(FSQRT_VL)
+ NODE_NAME_CASE(FCLASS_VL)
NODE_NAME_CASE(FMA_VL)
NODE_NAME_CASE(FCOPYSIGN_VL)
NODE_NAME_CASE(SMIN_VL)
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