[PATCH] D124976: [AArch64] Fix sub with carry

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3366
+      IsSigned ? overflowFlagToValue(Sum.getValue(1), VT1, DAG)
+               : carryFlagToValue(Sum.getValue(1), VT1, DAG, InvertCarry);
 
----------------
efriedma wrote:
> It's a bit concerning to me that you're changing OutFlag, but not OpCarryIn.  If we're inverting the output flag, don't we need to invert the input flag too?  Or is it already getting inverted correctly?
> 
> It might make sense to also add tests for i256 addition and subtraction.
Just checked; this is what we currently generate for i256 subtraction:

```
        subs    x0, x0, x4
        sbcs    x1, x1, x5
        cset    w8, hs
        cmp     w8, #1
        sbcs    x2, x2, x6
        cset    w8, hs
        cmp     w8, #1
        sbcs    x3, x3, x7
        ret
```

I guess maybe the input is already handled correctly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124976/new/

https://reviews.llvm.org/D124976