[PATCH] D125016: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions

[lizhijin via Phabricator via llvm-commits]

lizhijin created this revision.
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This patch changes the strategy for vectorizing freeze instrucion, from replicating multiple times to widening according to selected VF.


https://reviews.llvm.org/D125016

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/vector-freeze.ll


Index: llvm/test/Transforms/LoopVectorize/AArch64/vector-freeze.ll
===================================================================
--- /dev/null
+++ llvm/test/Transforms/LoopVectorize/AArch64/vector-freeze.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -loop-vectorize -mtriple aarch64-linux-gnu -S < %s | FileCheck %s
+; RUN: opt -loop-vectorize -mattr=+sve  -mtriple aarch64-linux-gnu -S < %s | FileCheck %s --check-prefix=SVE
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define void @test() #1 personality i8* undef {
+; CHECK-LABEL: @test(
+; CHECK:    freeze <16 x i8>
+; CHECK:    ret void
+;
+; SVE-LABEL: @test(
+; SVE:    freeze <vscale x 16 x i8>
+; SVE:    ret void
+;
+for.body.preheader:
+  br label %for.body
+
+for.body:                                         ; preds = %if.end, %for.body.preheader
+  %indvars.iv132 = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next133, %if.end ]
+  %arrayidx = getelementptr inbounds [1 x i8], [1 x i8]* undef, i64 0, i64 %indvars.iv132
+  %0 = load i8, i8* %arrayidx, align 1
+  br i1 false, label %if.end, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %for.body
+  %.fr122 = freeze i8 %0
+  %cmp9 = icmp eq i8 %.fr122, 0
+  br i1 %cmp9, label %if.end, label %switch.early.test
+
+switch.early.test:                                ; preds = %lor.lhs.false
+  br label %if.end
+
+if.end:                                           ; preds = %switch.early.test, %lor.lhs.false, %for.body
+  %indvars.iv.next133 = add nuw nsw i64 %indvars.iv132, 1
+  %exitcond136.not = icmp eq i64 %indvars.iv.next133, 0
+  br i1 %exitcond136.not, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:                                 ; preds = %if.end
+  ret void
+}
+
+attributes #0 = { argmemonly nofree nosync nounwind willreturn }
+attributes #1 = { "target-features"="+aes,+crypto,+neon,+sha2,+v8a" }
Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8423,6 +8423,7 @@
     case Instruction::URem:
     case Instruction::Xor:
     case Instruction::ZExt:
+    case Instruction::Freeze:
       return true;
     }
     return false;
@@ -9325,7 +9326,8 @@
   case Instruction::AShr:
   case Instruction::And:
   case Instruction::Or:
-  case Instruction::Xor: {
+  case Instruction::Xor:
+  case Instruction::Freeze: {
     // Just widen unops and binops.
     State.ILV->setDebugLocFromInst(&I);
 
@@ -9334,7 +9336,13 @@
       for (VPValue *VPOp : operands())
         Ops.push_back(State.get(VPOp, Part));
 
-      Value *V = Builder.CreateNAryOp(I.getOpcode(), Ops);
+      Value *V = nullptr;
+      if (I.getOpcode() == Instruction::Freeze) {
+        assert(Ops.size() == 1 && "Invalid number of operands!");
+        V = Builder.CreateFreeze(Ops[0]);
+      } else {
+        V = Builder.CreateNAryOp(I.getOpcode(), Ops);
+      }
 
       if (auto *VecOp = dyn_cast<Instruction>(V)) {
         VecOp->copyIRFlags(&I);


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