[PATCH] D124961: [riscv] Use X0 for destination of VSETVLI instruction if result unused

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D124961#3493925 <https://reviews.llvm.org/D124961#3493925>, @khchen wrote:

> I think maybe it's good to have pre-commit test to demonstrate VLS realistic cases could be benefited by this improvement, or at least mention realistic test are coming from VLS vectorization in commit message.

What does VLS stand for?

Assuming you mean fixed length vectorization, does the comment as submitted satisfy you?



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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1224
+    // through to check for VSETVLIs which write to an unused destination.
+    // For the non X0, X0 variant, we can replace the destination register
+    // with X0 to reduce register pressure.  This is really a generic
----------------
frasercrmck wrote:
> I know we have `PseudoVSETVLIX0`, but is it really an invariant that `PseudoVSETVLI` //never// has `X0, X0` at this stage? Should we maybe add an assert to be a bit more sure? If for whatever reason we do have `X0, X0` this would (subtly) generate some wrong code.
At this stage, all the operands are vregs.  We have tor rely on the register constraints that are on the instructions to cause the register allocator to do the right thing here.

The more generic version of this transform - not applied to just VSETVLI - would have to use register class constraints to on the def instead of using knowledge of the psuedo to assume x0 is valid as this one does.


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