[PATCH] D124894: Avoid 8 and 16bit switch conditions on x86

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 5 05:30:23 PDT 2022


spatel accepted this revision.
spatel added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1226
+  /// Returns preferred type for switch condition.
+  virtual MVT getSwitchConditionType(LLVMContext &Context,
+                                     EVT ConditionVT) const;
----------------
I'd put the "preferred" in the name itself to make the logic clear:
  getPreferredSwitchCondType(...)


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:33726
+  // zero-extensions.
+  if (ConditionVT.getSizeInBits() < 32) {
+    return MVT::i32;
----------------
Nit: can remove braces for one-line 'if'


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124894/new/

https://reviews.llvm.org/D124894



More information about the llvm-commits mailing list