[PATCH] D124960: [RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 4 13:54:00 PDT 2022

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reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124960/new/

https://reviews.llvm.org/D124960

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