[PATCH] D124894: Prefer 32bit and 64bit switch conditions for x86

Matthias Braun via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 4 13:20:05 PDT 2022


MatzeB added inline comments.


================
Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:1614
+  EVT OldVT = getValueType(DL, CondType);
+  MVT RegType = getRegisterType(Context, OldVT);
+  unsigned RegWidth = RegType.getSizeInBits();
----------------
MatzeB wrote:
> craig.topper wrote:
> > MatzeB wrote:
> > > craig.topper wrote:
> > > > If we just gave targets control over RegType here would that be enough?
> > > The callback is used by `CodeGenPrepare` though which deals with llvm IR and rather has `Type*`s than `MVT`s...
> > Ok could we return ExtType from the target and use ExtType to calculate RegWidth for `if` on 1617?
> > 
> > Realy, I'm wondering why we had to move all of the code into TargetLowering and duplicate Argument attributes checking in X86. Or is there some subtle difference that prevents us from sharing the Argument attribute handling.
> If you prefer we can share the logic starting at line 1632 (deciding between ZExt/SExt and the argument handling) simplifying the X86 callback with the drawback that targets can no longer opt-out of that logic (admittedly I don't know why they would want to opt-out, so I don't care too deeply).
Hmm we need an `MVT` if we want to have the `isSExtCheaperThanZExt` in the shared code as there's no equivalent callback for `Type*`...


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  https://reviews.llvm.org/D124894/new/

https://reviews.llvm.org/D124894



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