[llvm] fbaec11 - [SystemZ] Avoid crashing in tryRISBGZero().

Jonas Paulsson via llvm-commits llvm-commits at lists.llvm.org
Wed May 4 02:40:07 PDT 2022


Author: Jonas Paulsson
Date: 2022-05-04T11:38:50+02:00
New Revision: fbaec11683b5b9cac3dbca0a460ed871c774e7d7

URL: https://github.com/llvm/llvm-project/commit/fbaec11683b5b9cac3dbca0a460ed871c774e7d7
DIFF: https://github.com/llvm/llvm-project/commit/fbaec11683b5b9cac3dbca0a460ed871c774e7d7.diff

LOG: [SystemZ] Avoid crashing in tryRISBGZero().

Bail out from cases where the result is a ConstantSDNode as it cannot be
selected and should typically not end up here.

Fixes: #55204

Reviewed By: Ulrich Weigand

Added: 
    llvm/test/CodeGen/SystemZ/and-09.ll

Modified: 
    llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 4af0728b6cc39..161886f338142 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -968,7 +968,7 @@ bool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
     if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND &&
         RISBG.Input.getOpcode() != ISD::TRUNCATE)
       Count += 1;
-  if (Count == 0)
+  if (Count == 0 || isa<ConstantSDNode>(RISBG.Input))
     return false;
 
   // Prefer to use normal shift instructions over RISBG, since they can handle

diff  --git a/llvm/test/CodeGen/SystemZ/and-09.ll b/llvm/test/CodeGen/SystemZ/and-09.ll
new file mode 100644
index 0000000000000..320417984e8ea
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/and-09.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -o /dev/null -O0
+;
+; Check that tryRISBGZero() does not crash when LHS (and RHS) of an AND node
+; is constant.
+
+define void @fun() {
+  %const = bitcast i64 1064831134304126 to i64
+  %xor.i = xor i64 0, %const
+  %sub.i = add nsw i64 0, -1064831134304126
+  %xor1.i = xor i64 %sub.i, %const
+  %and.i = and i64 %xor1.i, %xor.i
+  %tobool5.not = icmp eq i64 %and.i, 0
+  %spec.store.select = select i1 %tobool5.not, i64 %const, i64 6
+  store i64 %spec.store.select, ptr undef
+  ret void
+}


        


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