[PATCH] D124836: [AArch64] Add support for -fzero-call-used-regs

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp:752
+#undef CASE
+  }
+}
----------------
void wrote:
> kristof.beyls wrote:
> > Just a drive-by comment: I'm wondering if SVE registers should also be listed here?
> I'm not familiar with the SVE registers (I assume you mean the `Z#` and `P#` ones). Could you give an example program?
SVE is slightly tricker here because the set of registers the caller must preserve depends on the signature of the function.

This is described here: https://github.com/ARM-software/abi-aa/blob/8a7b266879c60ca1c76e94ebb279b2dac60ed6a5/aapcs64/aapcs64.rst#613scalable-vector-registers

The callee-preserved registers are z8-z23 and p4-p15 if the function is using the VARIANT_PCS, the code for that condition in the asm printer is here:

https://github.com/llvm/llvm-project/blob/78fd413cf736953ac623cabf3d5f84c8219e31f8/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp#L864-L875


```
 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall ||
      MF->getFunction().getCallingConv() ==
          CallingConv::AArch64_SVE_VectorCall ||
      STI->getRegisterInfo()->hasSVEArgsOrReturn(MF)) {
```

Hope that helps a little.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D124836/new/

https://reviews.llvm.org/D124836