[PATCH] D124903: [X86][AMX][NFC] Replace PXOR instruction with SET0 in AMX pre config.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 3 22:14:32 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:393
         .addReg(Ymm);
   } else {
     assert(ST.hasSSE2() && "AMX should assume SSE2 enabled");
----------------
LuoYuanke wrote:
> craig.topper wrote:
> > Why is there no AVX1 code path to use VMOVUPSmr for 128 bits?
> I think usaully AMX imply AVX512 enabled, and for the correctness, it can be covered by SSE2 instruction MOVUPSmr. So I think AVX1 code path is nice to have, but not must.
We usually try not to mix AVX and SSE code due to the impact to the upper bits and how it affects the vzeroupper insertion. But I guess since these are stores they don't dirty the upper bits so maybe it isn't an impact.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124903/new/

https://reviews.llvm.org/D124903



More information about the llvm-commits mailing list