[llvm] dbe716e - [riscv] Add vsetvli tests involving moves to/from scalar regs

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-05-03T17:25:35-07:00
New Revision: dbe716e8741c20361054f08c53016e077a11c5b5

URL: https://github.com/llvm/llvm-project/commit/dbe716e8741c20361054f08c53016e077a11c5b5
DIFF: https://github.com/llvm/llvm-project/commit/dbe716e8741c20361054f08c53016e077a11c5b5.diff

LOG: [riscv] Add vsetvli tests involving moves to/from scalar regs

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index ebdb4f99e9df2..7449d91c9eaa6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -301,6 +301,55 @@ entry:
   ret <vscale x 1 x double> %f2
 }
 
+
+ at gdouble = external global double
+
+define <vscale x 1 x double> @test16(i64 %avl, double %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64, mf2, ta, mu
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.v.f v9, fa0
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v9, v8
+; CHECK-NEXT:    ret
+entry:
+  %vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)
+
+  %head = insertelement <vscale x 1 x double> poison, double %a, i32 0
+  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+  %f2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> undef,
+    <vscale x 1 x double> %splat,
+    <vscale x 1 x double> %b,
+    i64 %vsetvli)
+  ret <vscale x 1 x double> %f2
+}
+
+define double @test17(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test17:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32, mf2, ta, mu
+; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vfmv.f.s ft0, v8
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    vfmv.f.s ft1, v8
+; CHECK-NEXT:    fadd.d fa0, ft0, ft1
+; CHECK-NEXT:    ret
+entry:
+  %vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
+  %c1 = extractelement <vscale x 1 x double> %a, i32 0
+  %f2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> undef,
+    <vscale x 1 x double> %a,
+    <vscale x 1 x double> %b,
+    i64 %vsetvli)
+  %c2 = extractelement <vscale x 1 x double> %f2, i32 0
+  %c3 = fadd double %c1, %c2
+  ret double %c3
+}
+
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,