[llvm] 574ca03 - AMDGPU: Remove some invalid kill flags in tests

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-05-04T00:05:15+01:00
New Revision: 574ca03ef31fa364d98996406ef8f0ee1deb8dcd

URL: https://github.com/llvm/llvm-project/commit/574ca03ef31fa364d98996406ef8f0ee1deb8dcd
DIFF: https://github.com/llvm/llvm-project/commit/574ca03ef31fa364d98996406ef8f0ee1deb8dcd.diff

LOG: AMDGPU: Remove some invalid kill flags in tests

These killed registers need to be live out of the block but the
verifier wasn't catching it.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/optimize-compare.mir
    llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/optimize-compare.mir b/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
index a4c603346ba31..8cbc3b097b8e6 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
@@ -161,7 +161,7 @@ body:             |
   ; GCN-NEXT: bb.1:
   ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; GCN-NEXT: {{  $}}
-  ; GCN-NEXT:   S_CMP_EQ_I32 killed [[S_AND_B32_]], 1, implicit-def $scc
+  ; GCN-NEXT:   S_CMP_EQ_I32 [[S_AND_B32_]], 1, implicit-def $scc
   ; GCN-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN-NEXT:   S_BRANCH %bb.1
   ; GCN-NEXT: {{  $}}
@@ -181,7 +181,7 @@ body:             |
   bb.1:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
 
-    S_CMP_EQ_I32 killed %1:sreg_32, 1, implicit-def $scc
+    S_CMP_EQ_I32 %1:sreg_32, 1, implicit-def $scc
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.1
 
@@ -1403,7 +1403,7 @@ body:             |
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def dead $scc
-  ; GCN-NEXT:   S_CMP_EQ_U32 killed [[S_AND_B32_]], 0, implicit-def $scc
+  ; GCN-NEXT:   S_CMP_EQ_U32 [[S_AND_B32_]], 0, implicit-def $scc
   ; GCN-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN-NEXT:   S_BRANCH %bb.1
   ; GCN-NEXT: {{  $}}
@@ -1420,7 +1420,7 @@ body:             |
 
     %0:sreg_32 = COPY $sgpr0
     %1:sreg_32 = S_AND_B32 1, killed %0, implicit-def dead $scc
-    S_CMP_EQ_U32 killed %1:sreg_32, 0, implicit-def $scc
+    S_CMP_EQ_U32 %1:sreg_32, 0, implicit-def $scc
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.1
 
@@ -2008,7 +2008,7 @@ body:             |
 
     %0:sreg_32 = COPY $sgpr0
     %1:sreg_32 = S_AND_B32 2, killed %0, implicit-def dead $scc
-    S_CMP_EQ_U32 killed %1:sreg_32, 2, implicit-def $scc
+    S_CMP_EQ_U32 %1:sreg_32, 2, implicit-def $scc
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.1
 

diff  --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
index 24e1ec81cb3ad..35f4825eb2446 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
@@ -423,7 +423,7 @@ body:             |
     %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 
   bb.1:
-    $vcc = S_AND_B64 $exec, killed %2, implicit-def dead $scc
+    $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
     S_BRANCH %bb.2
 
@@ -475,7 +475,7 @@ body:             |
     %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
     %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec
     %2.sub0_sub1:sgpr_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
-    $vcc = S_AND_B64 $exec, killed %2.sub0_sub1:sgpr_128, implicit-def dead $scc
+    $vcc = S_AND_B64 $exec, %2.sub0_sub1:sgpr_128, implicit-def dead $scc
     S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
     S_BRANCH %bb.1