[PATCH] D124824: [RISCV] Make use of SHXADD instructions in RVV spill/reload code.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1760
                                                MachineInstr::MIFlag Flag) const {
   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
   assert(Amount % 8 == 0 &&
----------------
craig.topper wrote:
> I'm considering merging this with it's one caller. There might be some more optimization opportunities if we include the ADD/SUB to SP.
> 
> For example, vlenb * 7 + sp could become
> 
> ```
> csrrd a0, vlenb
> sub sp, sp, a0
> slli a0, a0, 3
> add sp, sp, a0
> ```
> 
> instead of
> 
> ```
> csrrd a0, vlenb
> slli a1, a0, 3
> sub a0, a1, a0
> add sp, sp, a0
> ```
> 
> That would save a temporary register.
Separate commit please.  :)

Any chance this could be done in a post-process combine like thing?  Duplicating what appears to be generic multiple improvements seems like poor code structure.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D124824/new/

https://reviews.llvm.org/D124824