[PATCH] D120958: [TableGen] Add support for variable length instruction in decoder generator

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

For the record, to get this to build with my downstream target, I had to add:

  MyInsnType MyInsnType::operator&(const uint64_t &RHS);
  bool MyInsnType::operator!=(const int &RHS);


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120958/new/

https://reviews.llvm.org/D120958