[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for the updates, I think this is looking good now.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17657
+  SDValue SUBS = N->getOperand(3);
+  SDValue Zero, CTTZ, AND;
+
----------------
I think AND is now unused.


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Comment at: llvm/test/CodeGen/AArch64/table-based-cttz.ll:1
+; RUN: llc -march=aarch64 < %s | FileCheck %s
+
----------------
Use -mtriple=aarch64. Otherwise I think this will run differently on non-aarch64 native machines.
Can you also run update_llc_test_checks on the file. It fills in all the check lines in a consistent way.
And maybe name the test file cttz-and.ll, or something like it. It isn't directly related with the table based cttz's.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782