[llvm] fe7d006 - [X86][AMX] Add mayLoad/mayStore property for AMX instructions.
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 3 00:04:55 PDT 2022
Author: Luo, Yuanke
Date: 2022-05-03T14:48:22+08:00
New Revision: fe7d0067bd355ff00b768e3ce8338018e5b104a5
URL: https://github.com/llvm/llvm-project/commit/fe7d0067bd355ff00b768e3ce8338018e5b104a5
DIFF: https://github.com/llvm/llvm-project/commit/fe7d0067bd355ff00b768e3ce8338018e5b104a5.diff
LOG: [X86][AMX] Add mayLoad/mayStore property for AMX instructions.
Added:
Modified:
llvm/lib/Target/X86/X86InstrAMX.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index d825981a6b365..368b05ee8db4b 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -48,14 +48,18 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
VEX, T8XD;
// Pseduo instruction for RA.
+ let mayLoad = 1 in
def PLDTILECFGV : PseudoI<(outs), (ins opaquemem:$src),
[(int_x86_ldtilecfg_internal addr:$src)]>;
+ let mayLoad = 1 in
def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
GR16:$src2,
opaquemem:$src3), []>;
+ let mayLoad = 1 in
def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
GR16:$src2,
opaquemem:$src3), []>;
+ let mayStore = 1 in
def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
GR16:$src2, opaquemem:$src3,
TILE:$src4), []>;
@@ -67,9 +71,12 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
let usesCustomInserter = 1 in {
// Pseudo instructions, using immediates instead of tile registers.
// To be translated to the actual instructions in X86ISelLowering.cpp
+ let mayLoad = 1 in
def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
+ let mayLoad = 1 in
def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
sibmem:$src2), []>;
+ let mayStore = 1 in
def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
[(int_x86_tilezero timm:$src)]>;
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