[PATCH] D124308: [MachineScheduler] exclude INLINEASM from schedule when it would increase register pressure

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineScheduler.cpp:459
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  DenseMap<const TargetRegisterClass *, unsigned> RCCount;
+
----------------
This is implicitly relying on register
Class exact matches when register classes are really overlapping sets 


================
Comment at: llvm/lib/CodeGen/MachineScheduler.cpp:473
+      LLVM_DEBUG(
+          dbgs() << "Not reschduling around: " << MI << "\nINLINEASM has "
+                 << it.second << " " << TRI->getRegClassName(it.first)
----------------
craig.topper wrote:
> reschduling -> rescheduling
Remove the new line and INLINEASM since that’s included with the instruction print (or Indent the rest)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124308/new/

https://reviews.llvm.org/D124308