[PATCH] D124771: [SDAG] fix miscompile when casting int->FP->int

[Sanjay Patel via Phabricator via llvm-commits]

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This is the codegen equivalent of D124692 <https://reviews.llvm.org/D124692>.

There's some (experimental?) app for verifying IR -> AArch asm, so the codegen tests can be used to exercise that.

As shown in https://github.com/llvm/llvm-project/issues/55150 - the existing fold may be wrong when converting to a signed value.
This is a quick fix to avoid the miscompile.
https://alive2.llvm.org/ce/z/KtaDmd

We could go further - there was no test coverage added for this group of folds with:
https://github.com/llvm/llvm-project/commit/3e0023b8f6277b4b1335214bdf5ea4a76005fe33 
...it seems to have been tacked on for completeness with respect to the IR transforms.
And I don't see any evidence that these patterns arise in SDAG, so we could delete the whole FoldIntToFPToInt() call.


https://reviews.llvm.org/D124771

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/float-conv-elim.ll
  llvm/test/CodeGen/X86/float-conv-elim.ll


Index: llvm/test/CodeGen/X86/float-conv-elim.ll
===================================================================
--- llvm/test/CodeGen/X86/float-conv-elim.ll
+++ llvm/test/CodeGen/X86/float-conv-elim.ll
@@ -82,12 +82,13 @@
   ret i32 %r
 }
 
+; This requires converting to FP and back.
+
 define i32 @s32_f32_s25_s32(i32 %a) {
 ; CHECK-LABEL: s32_f32_s25_s32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    shll $7, %eax
-; CHECK-NEXT:    sarl $7, %eax
+; CHECK-NEXT:    cvtsi2ss %edi, %xmm0
+; CHECK-NEXT:    cvttss2si %xmm0, %eax
 ; CHECK-NEXT:    retq
   %f = sitofp i32 %a to float
   %i = fptosi float %f to i25
@@ -107,12 +108,14 @@
   ret i32 %r
 }
 
+; TODO: This could avoid converting to FP.
+
 define i32 @u32_f32_s25_s32(i32 %a) {
 ; CHECK-LABEL: u32_f32_s25_s32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    shll $7, %eax
-; CHECK-NEXT:    sarl $7, %eax
+; CHECK-NEXT:    cvtsi2ss %rax, %xmm0
+; CHECK-NEXT:    cvttss2si %xmm0, %eax
 ; CHECK-NEXT:    retq
   %f = uitofp i32 %a to float
   %i = fptosi float %f to i25
Index: llvm/test/CodeGen/AArch64/float-conv-elim.ll
===================================================================
--- llvm/test/CodeGen/AArch64/float-conv-elim.ll
+++ llvm/test/CodeGen/AArch64/float-conv-elim.ll
@@ -45,10 +45,13 @@
   ret i32 %r
 }
 
+; This requires converting to FP and back.
+
 define i32 @s32_f32_s25_s32(i32 %a) {
 ; CHECK-LABEL: s32_f32_s25_s32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sbfx w0, w0, #0, #25
+; CHECK-NEXT:    scvtf s0, w0
+; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
   %f = sitofp i32 %a to float
   %i = fptosi float %f to i25
@@ -68,10 +71,13 @@
   ret i32 %r
 }
 
+; TODO: This could avoid converting to FP.
+
 define i32 @u32_f32_s25_s32(i32 %a) {
 ; CHECK-LABEL: u32_f32_s25_s32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sbfx w0, w0, #0, #25
+; CHECK-NEXT:    ucvtf s0, w0
+; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
   %f = uitofp i32 %a to float
   %i = fptosi float %f to i25
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15527,7 +15527,7 @@
   // This means this is also safe for a signed input and unsigned output, since
   // a negative input would lead to undefined behavior.
   unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned;
-  unsigned OutputSize = (int)VT.getScalarSizeInBits() - IsOutputSigned;
+  unsigned OutputSize = (int)VT.getScalarSizeInBits();
   unsigned ActualSize = std::min(InputSize, OutputSize);
   const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
 


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