[llvm] cb3fb08 - [AArch64] add tests for int->FP->int casts; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-05-02T09:18:12-04:00
New Revision: cb3fb085081c9cdf6eef6a51f0902064589d4ba6

URL: https://github.com/llvm/llvm-project/commit/cb3fb085081c9cdf6eef6a51f0902064589d4ba6
DIFF: https://github.com/llvm/llvm-project/commit/cb3fb085081c9cdf6eef6a51f0902064589d4ba6.diff

LOG: [AArch64] add tests for int->FP->int casts; NFC

Copied from x86 tests for multi-target coverage.
Also, provides coverage for target-specific asm
testing for Alive2 or its follow-ons.

See #55150 and D124692

Added: 
    llvm/test/CodeGen/AArch64/float-conv-elim.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/float-conv-elim.ll b/llvm/test/CodeGen/AArch64/float-conv-elim.ll
new file mode 100644
index 0000000000000..dcc543fd69f54
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/float-conv-elim.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-- < %s | FileCheck %s
+
+define i32 @s32_f32_s24_s32(i32 %a) {
+; CHECK-LABEL: s32_f32_s24_s32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #0, #24
+; CHECK-NEXT:    ret
+  %f = sitofp i32 %a to float
+  %i = fptosi float %f to i24
+  %r = sext i24 %i to i32
+  ret i32 %r
+}
+
+define i32 @s32_f32_u24_u32(i32 %a) {
+; CHECK-LABEL: s32_f32_u24_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w0, w0, #0xffffff
+; CHECK-NEXT:    ret
+  %f = sitofp i32 %a to float
+  %i = fptoui float %f to i24
+  %r = zext i24 %i to i32
+  ret i32 %r
+}
+
+define i32 @u32_f32_s24_s32(i32 %a) {
+; CHECK-LABEL: u32_f32_s24_s32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #0, #24
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %a to float
+  %i = fptosi float %f to i24
+  %r = sext i24 %i to i32
+  ret i32 %r
+}
+
+define i32 @u32_f32_u24_u32(i32 %a) {
+; CHECK-LABEL: u32_f32_u24_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w0, w0, #0xffffff
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %a to float
+  %i = fptoui float %f to i24
+  %r = zext i24 %i to i32
+  ret i32 %r
+}
+
+define i32 @s32_f32_s25_s32(i32 %a) {
+; CHECK-LABEL: s32_f32_s25_s32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #0, #25
+; CHECK-NEXT:    ret
+  %f = sitofp i32 %a to float
+  %i = fptosi float %f to i25
+  %r = sext i25 %i to i32
+  ret i32 %r
+}
+
+define i32 @s32_f32_u25_u32(i32 %a) {
+; CHECK-LABEL: s32_f32_u25_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf s0, w0
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    ret
+  %f = sitofp i32 %a to float
+  %i = fptoui float %f to i25
+  %r = zext i25 %i to i32
+  ret i32 %r
+}
+
+define i32 @u32_f32_s25_s32(i32 %a) {
+; CHECK-LABEL: u32_f32_s25_s32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w0, w0, #0, #25
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %a to float
+  %i = fptosi float %f to i25
+  %r = sext i25 %i to i32
+  ret i32 %r
+}
+
+define i32 @u32_f32_u25_u32(i32 %a) {
+; CHECK-LABEL: u32_f32_u25_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf s0, w0
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %a to float
+  %i = fptoui float %f to i25
+  %r = zext i25 %i to i32
+  ret i32 %r
+}