[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Can you make sure the diff is against current main branch, not against the last version of the patch.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17449
 
 static SDValue foldCTTZ(SDNode *N, SelectionDAG &DAG) {
   unsigned CC = N->getConstantOperandVal(2);
----------------
foldCTTZ -> foldCSELofCTTZ


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17471
+         "Illegal type in CTTZ folding");
+  if (isNullConstant(Zero) && isNullConstant(SUBS.getValue(1).getOperand(1))) {
+    SDValue X = CTTZ.getOpcode() == ISD::TRUNCATE
----------------
LLVM tends to prefer early exists, to reduce the indent level.

Instead of doing
```
if (X) {
  if (Y) {
    DoThing()
  }
}
```
it is  preferred to do
```
if (!X)
  return SDValue();
if (!Y)
  return SDValue();
DoThing()
```
In this case, the AND variable can be removed, for example.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782